New Waves of IoT Technologies Research – Transcending Intelligence and Senses at the Edge to Create Multi Experience Environments

The next wave of Internet of Things (IoT) and Industrial Internet of Things (IIoT) brings new technological developments that incorporate radical advances in Artificial Intelligence (AI), edge computing processing, new sensing capabilities, more security protection and autonomous functions accelerating progress towards the ability for IoT systems to self-develop, self-maintain and self-optimise. The emergence of hyper autonomous IoT applications with enhanced sensing, distributed intelligence, edge processing and connectivity, combined with human augmentation, has the potential to power the transformation and optimisation of industrial sectors and to change the innovation landscape. This chapter is reviewing the most recent advances in the next wave of the IoT by looking not only at the technology enabling the IoT but also at the platforms and smart data aspects that will bring intelligence, sustainability, dependability, autonomy, and will support human-centric solutions.acceptedVersio

Υλοποίηση του Υποσυστήματος Διαχείρισης Πολλαπλών Ουρών του Μεταγωγέα ATLAS I σε Full-Custom CMOS VLSI

The Quality of Service (QoS) requirements of contemporary networks lead to the use of sophisticated high-performance switching schemes; the primary ingredient of these is the maintenance and management of multiple queues of cells, which needs hardware implementation to achieve high speeds. This work consists of the design, in full-custom VLSI, of the majority of the queue management subsystem of ATLAS I. ATLAS I is a single-chip ATM switch with optional credit-based flow control. This 4-million-transistor chip is being designed and will be implemented in a 0.35 micron CMOS technology with 5 metal layers and 3.3V power supply, offering important features: 20 Gbit/s aggregate I/O throughput, a 256-cell pipelined shared memory, multicasting, and 3 levels of priorities. The queue management block of ATLAS I is a dual parallel pipeline that manages the multiple queues of ready cells, the per-flow-group credits, and the cells that are waiting for credits. These 3- and 4-stage pipelines, which handle events at the rate of one cell arrival or departure and one credit arrival per clock cycle, are using several multi-port memories, as well as some that can be searched by content. Two, three and four-port CAMs and SRAMs which support special access operations are laid out in full-custom. In addition, a new scheduling mechanism is incorporated in queue management, which arbitrates among flows arranged in groups rather than independently, providing fairness guarantees. The full-custom part of queue management contains approximately 65 thousand transistors in logic and 14 Kbits in various special memories, occupies 2.3 square-mm, consumes 270 mW (worst-case), and operates at 80 MHz (worst case) versus 50 MHz which is the required clock frequency to support the 622 Mb/s ATLAS I switch links.Οι απαιτήσεις για ποιότητα υπηρεσιών στα σύγχρονα δίκτυα οδηγούν στη χρήση μεταγωγέων υψηλής απόδοσης. Το πρωταρχικό απαραίτητο στοιχείο σ' αυτούς είναι η διατήρηση και η διαχείριση πολλαπλών ουρών, η οποία απαιτεί υλοποίηση σε hardware ώστε να επιτευχθούν υψηλές ταχύτητες. Αυτή η εργασία αποτελείται από τη σχεδίαση, σε full-custom VLSI, του μεγαλύτερου μέρους του υποσυστήματος διαχείρισης ουρών του ATLAS I. Το ATLAS I είναι ένας μεταγωγέας ΑΤΜ ολοκληρωμένος σε ένα chip με προαιρετικό έλεγχο ροής με βάση πιστώσεις. Αυτό το chip των 4 εκατομμυρίων transistors σχεδιάζεται και θα υλοποιηθεί σε τεχνολογία 0.35 μm CMOS, με 5 επίπεδα μετάλλου και τάση λειτουργίας 3.3 V, προσφέροντας σημαντικά πλεονεκτήματα, όπως συνολική παροχή 20 Gbit/s, κοινόχρηστη μνήμη 256 κυττάρων τύπου pipeline, 3 επίπεδα προτεραιότητας, και multicasting. Το τμήμα διαχείρισης ουρών του ATLAS I είναι μία διπλή παράλληλη pipeline, η οποία διαχειρίζεται τις πολλαπλές ουρές έτοιμων κυττάρων, τις πιστώσεις ανά ομάδα ροής, και τα κύτταρα που περιμένουν πίστωση. Αυτές οι pipelines των 3 και 4 βαθμίδων, οι οποίες χειρίζονται γεγονότα με ρυθμό μιάς άφιξης ή αναχώρησης κυττάρου και μιας άφιξης πίστωσης ανά κύκλο ρολογιού, χρησιμοποιούν πολύπορτες μνήμες, καθώς και μνήμες αναζήτησης βάσει περιεχομένου. Υλοποιήσαμε σε full-custom 3-πορτες και 4-πορ\-τες μνή\-μες CAM και SRAM που υποστηρίζουν ειδικούς τύπους προσπελάσεων. Επίσης, το τμήμα διαχείρισης ουρών περιέχει ένα νέο μηχανισμό χρονοπρογραμματισμού, ο οποίος διαιτητεύει μεταξύ ροών οργανωμένων σε ομάδες, παρέχοντας εγγυήσεις δικαιοσύνης. Το μέρος full-custom της διαχείρισης ουρών περιέχει περίπου 65 χιλιάδες τρανζίστορς σε λογική και 14 Kbits σε διάφορες ειδικές μνήμες, καταλαμβάνει χώρο 2.3 τετραγωνικά χιλιοστά, καταναλώνει 270 mWatt (στη χειρότερη περίπτωση), και λειτουργεί στα 80 MHz (στη χειρότερη περίπτωση), έναντι των 50 MHz που απαιτούνται για την υποστήριξη των συνδέσμων του μεταγωγέα στα 622 Mb/s

ATLAS II: Optimizing a 10Gbps Single-Chip ATM Switch

We describe ATLAS II, an optimized version of the ATLAS I ATM switch. While in ATLAS I we concentrated on correctness, in ATLAS II we concentrate on optimizing the area and the performance of the switch. To achieve these goals we utilize improved design techniques and circuitry, and we eliminate functionalities of marginal benefit. Our results show that we can achieve significant performance and cost benefits, requiring only a small increment in manpower. 1 Introduction Asynchronous Transfer Mode (ATM) networks have become mainstream for wide area networks (WANs) and also in local area networks. ATM was originally designed to carry realtime traffic and data, and as a consequence, ATM networks can efficiently handle voice, video and data making them ideal for multimedia-type applications. ATLAS I (ATm multi-LAne backpressure Switch One) is a high performance, single chip ATM switch designed in (the Computer Architecture and VLSI Systems Division, of the Institute of Computer Science of..

Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control

: We describe the queue management block of ATLAS I , a single-chip ATM switch (router) with optional credit-based (backpressure) flow control. ATLAS I is a 4-million-transistor 0.35-micron CMOS chip, currently under development, offering 20 Gbit/s aggregate I/O throughput, sub-microsecond cut-through latency, 256-cell shared buffer containing multiple logical output queues, priorities, multicasting, and load monitoring. The queue management block of ATLAS I is a dual parallel pipeline that manages the multiple queues of ready cells, the per-flow-group credits, and the cells that are waiting for credits. All cells, in all queues, share one, common buffer space. These 3- and 4-stage pipelines handle events at the rate of one cell arrival or departure per clock cycle, and one credit arrival per clock cycle. The queue management block consists of two compiled SRAM's, pipeline bypass logic, and multi-port CAM and SRAM blocks that are laid out in full-custom and support special access Cop..

The Memory Structures of ATLAS I, a High Performance, 16x16 ATM Switch Supporting Backpressure.

We present the overall structure of ATLAS I, emphasizing the memory use and requirements. We categorize these requirements in functionality and bandwidth and present the solutions we used in the first implementation of ATLAS I in a 0.35 CMOS technology. This implementation can serve as a starting point in the design of future switches with functionality similar to ATLAS I. 1. Introduction ATLAS I is a general-purpose, single-chip ATM switch with advanced architectural features. It is being developed within the ASICCOM 1 project. Figure 1 presents an overview of ATLAS I; it is a highly integrated 16x16 switch, with point-to-point serial links running at 622 Mbits/s each. Using link bundling, ATLAS I can also be configured as 8x8 at 1.25Gbps/link, or 4x4 at 2.5 Gbps/link, etc. The links run ATM on top of IEEE Std. 1355 "HIC/HS" [HIC95] as physical layer, using the BULL "STRINGS" GBaud serial-link transceiver [MCLN93]. 1 Funded by the European Union ACTS (Advanced Communication Te..

ATLAS II: οptimizing a 10Gbps σingle-chip ATM switch

Summarization: We describe ATLAS II, an optimized version of the ATLAS I ATM switch. While in ATLAS I we concentrated on correctness, in ATLAS II we concentrate on optimizing the area and the performance of the switch. To achieve these goals we utilize improved design techniques and circuitry, and we eliminate functionalities of marginal benefit. Our results show that we can achieve significant performance and cost benefits, requiring only a small increment in manpowerΠαρουσιάστηκε στο: 12th Annual 1999 IEEE International ASIC/SOC Conferenc

Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control

ABSTRACT: We describe the queue management block of ATLAS I, a single-chip ATM switch (router) with optional credit-based (backpressure) flow control. ATLAS I is a 4-million-transistor 0.35-micron CMOS chip, currently under development, offering 20 Gbit/s aggregate I/O throughput, sub-microsecond cut-through latency, 256-cell shared buffer containing multiple logical output queues, priorities, multicasting, and load monitoring. The queue management block of ATLAS I is a dual parallel pipeline that manages the multiple queues of ready cells, the per-flow-group credits, and the cells that are waiting for credits. All cells, in all queues, share one, common buffer space. These 3- and 4-stage pipelines handle events at the rate of one cell arrival or departure per clock cycle, and one credit arrival per clock cycle. The queue management block consists of two compiled SRAM’s, pipeline bypass logic, and multi-port CAM and SRAM blocks that are laid out in full-custom and support special acces